Senior Physical Design Engineer
Experience: 5-10 years
Responsibilities:
- Responsible for physical design implementation of complex SoCs
- Participating in physical design methodologies and flow automation
- Floorplan, place, route, signal integrity avoidance/fixing, power/clock distribution, timing closure - timing, power, clock and noise analysis and DRC/LVS
Senior Verification Engineer (Specman tool)
Requirements:
-Fullchip verification testbench and environment creation and for multi-million gate ASIC/SOC.
-Must be highly proficient with Specman
-Ability to write design specs for components and modules in the verification environment (test benches, system models, etc.)
-Real experience with few protocols like USB2.0, PCI-Express, Utopia, SPI, DDR Memory controller, EIO, SATA or POS-PHY
US work permission required
contact: sophia@synapse-da.com
Experience: 5-10 years
Responsibilities:
- Responsible for physical design implementation of complex SoCs
- Participating in physical design methodologies and flow automation
- Floorplan, place, route, signal integrity avoidance/fixing, power/clock distribution, timing closure - timing, power, clock and noise analysis and DRC/LVS
Senior Verification Engineer (Specman tool)
Requirements:
-Fullchip verification testbench and environment creation and for multi-million gate ASIC/SOC.
-Must be highly proficient with Specman
-Ability to write design specs for components and modules in the verification environment (test benches, system models, etc.)
-Real experience with few protocols like USB2.0, PCI-Express, Utopia, SPI, DDR Memory controller, EIO, SATA or POS-PHY
US work permission required
contact: sophia@synapse-da.com