本文发表在 rolia.net 枫下论坛we need a verification engineer urgently using specman tools and physical design engineer (first encounter, calibre or astro/apollo). Any one interested, pls. leave you contact info or send me email at bullyaya@yahoo.com
you must have US working permission first.
Senior Physical Design Engineer Magma, Cadence or Synopsys
Experience: 5-10 years
Responsibilities: - Responsible for physical design implementation of complex SoCs
- Participating in physical design methodologies and flow automation
- Floorplan, placeand route, signal integrity avoidance/fixing, power/clock distribution, timing closure - timing, power, clock and noise analysis and DRC/LVS
Minimum Requirements:
- BSEE, MSEE preferred
- 2+ years of experience in block and chip level physical design in 0.13u or 90u technology.
- Must have successful track record taping out complex chips (min 2M gates) using Magma, Cadence or Synopsys P&R tools
- Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, antenna etc.)
- Prior experience in design timing closure, clock/power distribution and analysis, RC Extraction, place and route.
- Hands on experience in running static timing analysis (STA) tools like primetime (PT-SI). Circuit level comprehension of time critical paths in the design
- Should be a power user of P&R and analysis tools from Magma(Blast Fusion, Blast Create), Synopsys (Primetime, STAR-RCXT), Mentor (Calibre)
- Coding experience in C++, C, Perl and TCL a big plus
Senior Verification Engineer
Experience: 5-10 years
Requirements:
-Fullchip verification testbench and environment creation and for multi-million gate ASIC/SOC.
-Must be highly proficient with Specman or Verilog, Vera, SystemC
-Ability to write design specs for components and modules in the verification environment (test benches, system models, etc.)
-Must have real experience with few protocols like USB2.0, PCI-Express, Utopia, SPI, DDR Memory controller, EIO, SATA or POS-PHY -Should have excellent self-driven capabilities " to lead a projects verification.
Minimum Requirements:
-BSEE, MSEE preferred
-Min 5yr experience in verification更多精彩文章及讨论，请光临枫下论坛 rolia.net
you must have US working permission first.
Senior Physical Design Engineer Magma, Cadence or Synopsys
Experience: 5-10 years
Responsibilities: - Responsible for physical design implementation of complex SoCs
- Participating in physical design methodologies and flow automation
- Floorplan, placeand route, signal integrity avoidance/fixing, power/clock distribution, timing closure - timing, power, clock and noise analysis and DRC/LVS
Minimum Requirements:
- BSEE, MSEE preferred
- 2+ years of experience in block and chip level physical design in 0.13u or 90u technology.
- Must have successful track record taping out complex chips (min 2M gates) using Magma, Cadence or Synopsys P&R tools
- Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, antenna etc.)
- Prior experience in design timing closure, clock/power distribution and analysis, RC Extraction, place and route.
- Hands on experience in running static timing analysis (STA) tools like primetime (PT-SI). Circuit level comprehension of time critical paths in the design
- Should be a power user of P&R and analysis tools from Magma(Blast Fusion, Blast Create), Synopsys (Primetime, STAR-RCXT), Mentor (Calibre)
- Coding experience in C++, C, Perl and TCL a big plus
Senior Verification Engineer
Experience: 5-10 years
Requirements:
-Fullchip verification testbench and environment creation and for multi-million gate ASIC/SOC.
-Must be highly proficient with Specman or Verilog, Vera, SystemC
-Ability to write design specs for components and modules in the verification environment (test benches, system models, etc.)
-Must have real experience with few protocols like USB2.0, PCI-Express, Utopia, SPI, DDR Memory controller, EIO, SATA or POS-PHY -Should have excellent self-driven capabilities " to lead a projects verification.
Minimum Requirements:
-BSEE, MSEE preferred
-Min 5yr experience in verification更多精彩文章及讨论，请光临枫下论坛 rolia.net